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ADM1175
Data Sheet
WRITE EXTENDED COMMAND BYTE
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
7.
8.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
device, as follows:
1
2
3
4
5
6
7 8
SLAVE
REGISTER
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the register address byte. The MSB of
this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended
registers is to be written to (see Table 8). All other bits
should be set to 0.
The slave asserts an acknowledge on SDA.
The master sends the extended command byte (see
EXTENDED
S ADDRESS W A ADDRESS A COMMAND A P
BYTE
Figure 37. Write Extended Byte
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended Register
0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0 0 0 0 0 1 1 CONTROL
Table 9, Table 10, and Table 11).
Table 9. ALERT_EN Register Operations
Bit
0
Default
0
Name
EN_ADC_OC1
Function
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH
register.
1
0
EN_ADC_OC4
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the ALERT_TH
register.
2
1
EN_HS_ALERT
Enabled if the hot swap operation either latches off or enters a cooldown cycle because of an
overcurrent event.
3
0
EN_OFF_ALERT
Enables an alert if the hot swap operation is turned off by a transition that deasserts the ON/ONB pin or
by an operation that writes the SWOFF bit high.
4
0
CLEAR
Clears the OFF_ALERT, HS_ALERT, and ADC_ALERT status bits in the STATUS register. The value of these
bits may immediately change if the source of the alert is not cleared and the alert function is not
disabled. The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit
[7:0]
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit value
corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
LSB, forces the hot swap operation off. Equivalent to deasserting the ON/ONB pin.
Rev. C | Page 18 of 24
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